Steady advances in integrated circuit technology have fueled the last 30 years of increasingly rapid progress with regard to the speed and complexity of signal processing circuitry design. In the past, system processing speed was determined by gate and register performance. Thus, to increase the speed and power of a particular circuit, one might simply select faster, more complex, and even less expensive integrated circuits.
Given these circumstances, analog circuit design issues, such as crosstalk, phase distortion, amplitude distortion, reflections, ringing, and ground bounce could be safely ignored. At worst, such events were treated as minor irritants, since they rarely arose. This was the case because synchronous digital logic is fairly forgiving with regard to amplitude and timing variations, especially at slow clock speeds. Times and circumstances have changed. At current operational design speeds, analog circuit characteristics play a strong, if not dominating role in determining overall digital system performance.
Integrated circuit packaging also affects high speed performance. Almost all packages, when used at high speed, suffer from problems with lead inductance and lead capacitance. The inductance of individual leads in a device package creates a problem called ground bounce. This phenomenon causes glitches to arise in logic inputs whenever the device outputs switch from one state to another, especially if they are subjected to heavy capacitive loading. The magnitude of the glitches, and the effects they have, are a subject of concern to the high speed circuit designer.
Ground bounce has become such a problem that many articles have been written about the subject, and various approaches have been taken to model its occurrence. See, for example, Analyzing Crosstalk and Ground Bounce in Multiconductor Systems Using SPICE Circuit Simulations by A. W. Barr, published in the AMP Journal of Technology, Vol. 3, November 1993.
To understand how ground bounce occurs, reference is now made to FIG. 1, in which is shown a prior art schematic view of an idealized logic die, wire-bonded to four leads of an integrated circuit package. One transmit circuit 150 and one receive circuit 145 are also illustrated. The transmit circuit 150 shown includes a totem-pole output stage, although any configuration may exhibit the same problem as described above at high operational speeds.
Assume that the capacitor 155 is charged, and that the lower output driver switch closes, discharging the capacitor 155 to ground 130. As the voltage across the capacitor 155 falls, the stored charge flows back to the ground 130, causing a massive current surge to flow around the ground loop shown as Idischarge. As the current Idischarge builds and then recedes, changes in the current Idischarge, flowing through the inductance Lgnd 125 of the ground pin 120, induce a voltage Vgnd between the system ground plane 130 underneath the device 110 and the internal package ground domain 135. The magnitude of this voltage is: Vgnd=Lgnd*(d/dt)Idischarge. It is the shift in this internal ground reference voltage Vgnd due to output switching that is called “ground bounce.”
The ground bounce voltage Vgnd is usually small compared to the full-swing output voltage across the load 155. While the voltage Vgnd typically does not act to significantly impair the transmitted signal from the driver, it can interfere in a major way with signal reception.
Consider the receiver section 145 of the same die. The receiver 140 shown differentially compares the input voltage against its local internal ground reference. This differencing operation appears in FIG. 1 as a plus (+) input connected to the Vin lead 115 and a minus (−) input connected to the internal ground domain 135. Because the internal ground domain 135 carries the Vgnd noise pulse, the actual differential voltage seen by the input circuit is equal to: Vactual=Vin−Vgnd.
Because the input circuit receiver 140 responds to the difference between the plus (+) and minus (−) inputs, there is no way to know whether the noise pulse Vgnd has been added to the minus (−) input, or subtracted from the plus (+) input. In other words, the Vgnd pulse voltage appears to the input circuitry 145 as if it were noise superimposed directly on the desired input signal, Vin. Moreover, if N outputs are simultaneously switched from an integrated circuit chip package into N corresponding capacitive loads, the amount of ground current will be increased by N times, and the magnitude of the Vgnd pulse will be increased accordingly.
The magnitude of the ground bounce voltage Vgnd is proportional to the rate of change of the magnitude of current passing through the ground pin 120. When capacitive loads are driven, the rate of change in the current appears as the second derivative of the voltage, which is typically described as a double-humped waveform, or a single sine-wave cycle, first bumping up, and then bumping down.
Ground bounce voltages can affect circuits in many significant ways. For example, referring now to FIG. 2A, a prior art view of a typical TTL address driver circuit can be seen. The circuit 205 includes a TTL octal D flip-flop 210, with a single clock input 230 driving an address bus 220 connected to a bank of memory chips 225. If there are 32 memory chips in the bank 225, and each memory chip in the bank 225 presents a 5 pF capacitive load at each address input, then each address line will see a total capacitive loading of about 160 pF.
FIG. 2B illustrates the operational effect of the circuit in FIG. 2A. Assume that data arrives at the data input 215 with plenty of setup time 282 but with little hold time 284. For example, as shown in FIG. 2B, illustrating a prior art view of ground bounce activity and its effect on the typical circuit illustrated in FIG. 2A, the data may arrive at the input 215 with a 3-ns setup time 282 and a 1-ns hold time 284. On the first rising clock edge 292 the flip-flop 210 latches the data input 252 word “FF” 254. At the second rising clock edge 294 the flip-flop 210 latches the data input 252 word “00” 256. In each case, the flip-flop propagation delay 280 of 3-ns is slightly longer than the required hold time 284. As the input data 258 changes to some other pattern at time 296, which follows 1-ns after the second rising clock edge 294, the flip-flop 210 has internally latched the “00” data word 256, but the outputs 272 have not yet switched from “FF” 272 to “00” 274.
The Vgnd trace 262 demonstrates that after the first rising clock edge 292, when the outputs 250 switch to a positive value 272, charging current flows in the power pin of the flip-flop 210, and not into the ground pin, so little noise appears on the trace 262 at point 269. However, at time 298, as all eight outputs swing to a LOW value 274, a large noise pulse 266 appears on the Vgnd trace 262. This noise pulse 266 causes an error known as double-clocking within the flip-flop 210, and is well known to those skilled in the art.
Double-clocking results from differential input action in the clock circuit of the flip-flop 210, which measures the voltage difference between the chip's clock pin 230 and its ground pin. The Clock−Vgnd voltage difference trace 264 of FIG. 2B shows this difference, which is representative of TTL circuits. CMOS circuits tend to compare inputs against a weighted average of Vcc (i.e., the operational supply voltage) and ground, while other logic families simply compare inputs against Vcc. However, in each case, the same problems arise, albeit with slightly different topologies.
The difference trace 264 waveform shows a clean clock edge 261 at the time of the first rising edge 292 of the clock waveform 260, followed by a glitch 268 induced by signal currents flowing into the flip-flop 210 ground pin. The glitch 268 will cause the flip-flop to re-clock; if the data input 215 has changed by the time the glitch 268 occurs, the flip-flop 210 will proceed directly to the unknown state “XX” 276. The outputs 250 at this point in time will momentarily flip to the correct state “00” 274, and then mysteriously flop to the unknown (incorrect) condition “XX” 276. The problem is compounded because external observations of the clock input 230 will typically reveal a perfectly clean signal. It is only by viewing internal logic package signals that one may locate the problem.
Double-clocking errors typically occur within dual-inline flip-flop packages that have fast output drivers connected to heavy capacitive loads. Edge-sensitive input lines, such as resets and interrupt service lines, are particularly susceptible to ground bounce glitches.
Thus, given the ever-increasing clock speeds used in current designs, there is a need in the art to characterize ground bounce signals, both as to their magnitude and shape. Referring now to FIG. 3, a prior art view of a system to measure ground bounce voltage with respect to an integrated circuit package can be seen. In this case, the system 300 is set up to attempt measurement of the ground bounce voltage Vgnd for a quad flip-flop 310, such as a 74HC174 flip-flop, which is configured so that three of the outputs 370 are toggled between HIGH and LOW values, while the fourth output 380 is fixed at a LOW value. Capacitive loads 360 can thus be applied to any of the three active outputs 370. This prior art arrangement can therefore be used to measure ground bounce voltage Vgnd with a variety of loads.
Because the inactive fourth output 380 is fixed at a logic LOW value, it can serve as a crude window into the chip 310 through which the internal ground voltage may be measured. The clock 340 and asynchronous reset 350 lines are used to alternately set and reset the three active outputs 370, in a manner well known to those skilled in the art.
With all three capacitive loads 360 connected (assume a value of 20 pF per load), the magnitude of the ground bounce voltage Vgnd 397, as measured using a probe 390 on the inactive output 380, and viewed on an oscilloscope 395, is about 150 mV. While this may seem not very significant, consider that the low-side voltage margin on some types of High-Speed Complementary Metal Oxide Semiconductor (HCT) logic is only about 470 mV. If, for example, eight simultaneous outputs were switching, the magnitude of the pulse 397 would be larger by a factor of 8/3, reaching a value of 400 mV. Moreover, the magnitude of Vgnd reduces the available residual noise margin which might be used to compensate for other noise and signal distortion effects.
Thus, as circuit clock speeds increase, there is an increasing need to characterize the magnitude and shape of the ground bounce voltage. However, integrated circuit packages do not always lend themselves to the prior art testing methods previously described. Such methods are error-prone, introducing inductance and capacitance via the probes required to make the measurement, as well as being susceptible to the proximity of other signals outside of the chip whose performance is being scrutinized. Moreover, the package itself introduces errors due to parasitic capacitance, such that measurements taken outside of the package differ from what truly exists on the surface of the die. These considerations give rise to a need in the art for improved apparatus, systems, and methods of measuring the magnitude and shape of the ground bounce voltage under various conditions. Such apparatus, systems, and methods should obviate the need for external measurement circuitry, probes, and test apparatus, if possible, and consistently improve the accuracy of ground bounce voltage characterization measurements.